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19-0546; Rev 0; 5/06
12V/5V Input Buck PWM Controller
General Description
The MAX5951 is a 12V pulse-width modulated (PWM), step-down, DC-DC controller. The device operates over the input-voltage range of 8V to 16V or 5V 10%, and provides an adjustable output from 0.8V to 5.5V. The device delivers up to 10A of load current with excellent load-and-line regulation. The MAX5951 PWM section utilizes a voltage-mode control scheme for good noise immunity and offers external compensation, allowing for maximum flexibility with a wide selection of inductor values and capacitor types. The device operates at a fixed switching frequency that is programmable from 100kHz to 1MHz and can be synchronized to an external clock signal though the SYNCIN input. The device includes undervoltage lockout (UVLO) and digital soft-start. Protection features include lossless valley-mode current limit, hiccup-mode output short-circuit protection, and thermal shutdown. The MAX5951 is available in a space-saving 5mm x 5mm, 32-pin thin QFN package and is specified for operation over the -40C to +85C extended temperature range. Refer to the MAX5950 data sheet for a pincompatible PWM controller with hot swap.
Features
8V to 16V or 5V 10% Input-Voltage Range Lossless Valley-Mode Current Sensing Output Voltage Adjustable from 0.8V to 5.5V Voltage-Mode Control External Compensation for Maximum Flexibility Digital Soft-Start Sequencing or Ratiometric Tracking Startup Synchronization Programmable PGOOD Output Programmable Switching Frequency from 100kHz to 1MHz External Frequency Synchronization SYNCIN and SYNCOUT Enable 180 Out-of-Phase Operation Thermal Shutdown and Short-Circuit Protection Space-Saving, 5mm x 5mm, 32-Pin TQFN Package
MAX5951
Ordering Information
PART MAX5951ETJ+ TEMP RANGE -40C to +85C PINPACKAGE 32 TQFN PKG CODE T3255-4
Applications
PCI-e Express ModulesTM General 12V or 5V Input PWM Controllers Blade Servers RAID Base Stations Workstations
+Denotes lead-free package.
Pin Configuration
ILIM CS+
TOP VIEW
STARTUP 18
PGOOD
SENSE
COMP
24 CS- 25 PGND 26 DL 27 DREG 28 LX 29 DH 30 BST 31 REG 32
23
22
21
FB
20
19
17 16 15 14 13 SYNCIN SYNCOUT AGND THRESH DCENI N.C. N.C. N.C.
MAX5951
RT 12 11 10 9 8 N.C.
+
1 IN 2 PUVLO 3 N.C. 4 N.C. 5 IN 6 N.C. 7 N.C.
PCI-e Express Modules is a trademark of PCI-SIG.
TQFN (5mm x 5mm) ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
12V/5V Input Buck PWM Controller MAX5951
ABSOLUTE MAXIMUM RATINGS
IN to AGND.............................................................-0.3V to +24V BST to AGND..........................................................-0.3V to +30V BST to LX..................................................................-0.3V to +6V CS- to AGND ...............................................-0.3V to (VIN + 0.3V) REG, DREG, PUVLO, DCENI, SYNCIN, THRESH, SENSE to AGND....................................................-0.3V to +6V RT, ILIM, STARTUP, PGOOD, FB, CS+ to AGND ....-0.3V to +6V SYNCOUT, COMP to AGND.....................-0.3V to (VREG + 0.3V) DL to PGND...............................................-0.3V to (VDREG + 6V) DH to LX ....................................................-0.3V to (VBST + 0.3V) PGND to AGND .....................................................-0.3V to +0.3V Input Current (any pin) .....................................................50mA Continuous Power Dissipation (TA = +70C) 32-Pin TQFN (derate 34.5 mW/C above +70C) .2758.6mW 32-Pin TQFN (JA) ....................................................+29C/W 32-Pin TQFN (JC) ...................................................+2.1C/W Operating Ambient Temperature Range .............-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 12V or VIN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 100k, RILIM = 60k, CREG = 2.2F, TA = TJ = -40C to +85C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER Input-Voltage Range Standby Supply Current Quiescent Supply Current Switching Supply Current PWM UVLO Default PWM Undervoltage Lockout Threshold PWM Undervoltage Lockout Hysteresis PUVLO Threshold PUVLO Hysteresis PUVLO Input Impedance PWM DCENI CONTROL DCENI Comparator Input Common-Mode Range DCENI Comparator Offset DCENI Comparator Hysteresis DCENI Input Current THRESH Operating Voltage Range THRESH Input Current Default DCENI Threshold VTHRESH > 0.6V VTHRESH < 0.3V VTHRESH < 0.3V -1 0.6 -1.5 -5 1.202 1.22 VDCENI - VTHRESH 0 -10 100 +1 2.5 +1 +1 1.238 3 +10 V mV mV A V A V 180 VPUVLO VPUVLO rising 1.202 VIN rising 6.7 0.7 1.220 122 310 500 1.238 7.3 V V V mV k SYMBOL VIN CONDITIONS VIN = VREG = VDREG (Note 2) VIN = 16V, VPUVLO = 0V VIN = 16V, VFB = 0.9V VIN = 16V, VFB = 0V MIN 8 4.5 0.3 1.6 5.0 TYP MAX 16 5.5 0.5 2.6 8.0 UNITS V mA mA mA
2
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12V/5V Input Buck PWM Controller
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V or VIN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 100k, RILIM = 60k, CREG = 2.2F, TA = TJ = -40C to +85C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER PWM PGOOD OUTPUT SENSE Threshold SENSE Hysteresis SENSE Input Bias Current PGOOD Internal Pullup Current PGOOD Output Voltage Low INTERNAL VOLTAGE REGULATOR Output Voltage Set Point Line Regulation Load Regulation PWM OSCILLATOR Oscillator Frequency Range fSW VSYNCIN = 0V, fSW = 5 x 1010 / RRT Hz TA = TJ = +25C Oscillator Accuracy TA = TJ = -40C to +85C RT Voltage Maximum Duty Cycle SYNCIN High-Level Voltage SYNCIN Low-Level Voltage SYNCIN Pulldown Resistor SYNCIN Rising to SYNCOUT Falling Delay SYNCIN Falling to SYNCOUT Rising Delay Maximum SYNCIN Frequency SYNCOUT Voltage High SYNCOUT Voltage Low PWM ERROR AMPLIFIER FB Input Range FB Input Current COMP Output Voltage Range Open-Loop Gain Unity-Gain Bandwidth Reference Voltage fGBW VREF ICOMP = -500A to +500A 792 ICOMP = -500A to +500A 0 -250 0.25 80 2.5 800 808 VREF +250 VREG 0.5 V nA V dB MHz mV VHSYNCOUT ISYNCOUT = +1.2mA VLSYNCOUT ISYNCOUT = -2.4mA 1 VREG 0.1 50 50 100 10 30 VRT 50k < RRT < 500k VSYNCIN = 0V, VIN = 12V 82 2.1 0.8 150 fSW < 500kHz fSW > 500kHz fSW < 500kHz fSW > 500kHz 100 -2.5 -4 -3.5 -5 2 88 1000 +2.5 +4 +3.5 +5 kHz % % V % V V k ns ns MHz V mV VREG VIN = 8V to 16V IREG = 0 to 50mA 4.7 5.3 1 150 V mV/V mV IPGOOD = -2.4mA -1 10 50 VSENSE rising 788 800 100 +1 812 mV mV A A mV SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5951
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3
12V/5V Input Buck PWM Controller MAX5951
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V or VIN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 100k, RILIM = 60k, CREG = 2.2F, TA = TJ = -40C to +85C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER PWM COMPARATOR Comparator Offset Voltage Comparator Propagation Delay PWM DIGITAL SOFT-START Soft-Start Duration Reference Voltage Steps PWM RAMP GENERATOR Ramp Amplitude PWM CURRENT-LIMIT COMPARATOR AND HICCUP MODE Cycle-by-Cycle Valley CurrentLimit Threshold Adjustment Range Cycle-by-Cycle Valley CurrentLimit Threshold Tolerance ILIM Reference Current ILIM Reference Current Tempco CS+, CS- Input Bias Current PWM HICCUP MODE Number of Cumulative CurrentLimit Events to Hiccup Number of Consecutive Noncurrent-Limit Cycles to Clear NCL Hiccup Timeout PWM STARTUP INPUT STARTUP Threshold STARTUP Threshold Hysteresis Internal Pullup Current STARTUP Output Voltage Low PWM DH DRIVER Peak Source Current Peak Sink Current DH Resistance Sourcing DH Resistance Sinking VDH,LX = 0V, pulse width < 100ns, VBST,LX = 5V VDH,LX = 5V, pulse width < 100ns, VBST,LX = 5V IDH = 50mA, VBST,LX = 5V IDH = -50mA, VBST,LX = 5V 2 2 1 1 3 3 A A ISTART ISTARTUP = -2.4mA VSUT 1.1 250 10 0.1 1.9 V mV A V NCL 8 Clocks VCS+ = 0V, VCS- = -0.3V, current out of the CS_ -1 Limit = VILIM / 10 VILIM = 0.5V VILIM = 3.5V VILIM = 0 to 3.5V, TA = TJ = +25C 50 44.5 330 19 20 3333 +20 350 55.5 366 21 mV 1.8 V 1024 128 6.3 Clocks Steps mV 0.3 40 V ns SYMBOL CONDITIONS MIN TYP MAX UNITS
mV A ppm/C A
NCLR NHT
3 512
Clocks Clocks
4
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12V/5V Input Buck PWM Controller
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V or VIN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 100k, RILIM = 60k, CREG = 2.2F, TA = TJ = -40C to +85C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER PWM DL DRIVER Peak Source Current Peak Sink Current DL Resistance Sourcing DL Resistance Sinking Break-Before-Make Time THERMAL SHUTDOWN Thermal Shutdown Temperature Thermal Shutdown Hysteresis TJ rising 135 15 C C VDL = 0V, pulse width < 100ns, VDREG = 5V VDL = 5V, pulse width < 100ns, VDREG = 5V IDL = 50mA, VDREG = 5V IDL = -50mA, VDREG = 5V 2 2 1 1 25 3 3 A A ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5951
Note 1: Limits at -40C are guaranteed by design and are not production tested. Note 2: For 5V applications, connect REG directly to IN.
Typical Operating Characteristics
(Typical Operating Circuits. VIN = 12V or VIN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 49.9k, RILIM = 48.7k, CREG = 2.2F, TA = +25C.)
DEFAULT DCENI THRESHOLD vs. TEMPERATURE
MAX5951 toc01
SENSE THRESHOLD vs. TEMPERATURE
MAX5951 toc02
REG OUTPUT VOLTAGE vs. TEMPERATURE
MAX5951 toc03
1.30
808
5.15 5.10 5.05 VREG (V)
1.27 DCENI THRESHOLD (V)
1.24
SENSE THRESHOLD (mV)
804
800
5.00 4.95
1.21
796
1.18
792
4.90 4.85 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
1.15 -40
-15
10
35
60
85
788 -40
TEMPERATURE (C)
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5
12V/5V Input Buck PWM Controller MAX5951
Typical Operating Characteristics (continued)
(Typical Operating Circuits. VIN = 12V or VIN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 49.9k, RILIM = 48.7k, CREG = 2.2F, TA = +25C.)
REG OUTPUT VOLTAGE vs. LOAD CURRENT
MAX5951 toc04
REG OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX5951 toc05
SWITCHING FREQUENCY vs. RRT
900 800 700 fSW (kHz)
MAX5951 toc06a
5.15 5.10 5.05 VREG (V)
5.06
1000
5.04
VREG (V)
5.02
600 500 400
5.00 4.95 4.90 4.85 0 10 20 30 40 50 IREG (mA)
5.00
4.98
300 200
4.96 8 10 12 PWM_IN (V) 14 16
100 50 100 150 200 250 300 350 400 450 500 RRT (k)
SWITCHING PERIOD vs. RRT
MAX5951toc06b
SWITCHING FREQUENCY vs. TEMPERATURE
MAX5951 toc07
FB REFERENCE VOLTAGE vs. TEMPERATURE
MAX5951 toc08
10 9 SWITCHING PERIOD (s) 8 7 6 5 4 3
1030 RRT = 49.9k 1020 1010 1000 990 980
808
804
VREF (mV) -40 -15 10 35 60 85
fSW (kHz)
800
796
792
2 1 50 100 150 200 250 300 350 400 450 500 RRT (k) 970 TEMPERATURE (C) 788 -40 -15 10 35 60 85
TEMPERATURE (C)
OPEN-LOOP GAIN/PHASE vs. FREQUENCY
VALLEY CURRENT-LIMIT THRESHOLD (mV) 100 90 80 70 GAIN (dB) 60 50 40 30 20 10 0 -10 -20 0 10 100 1k 10k 100k 1M FREQUENCY (Hz)
MAX5951 toc09
VALLEY CURRENT-LIMIT THRESHOLD vs. VILIM
MAX5951 toc10
VALLEY CURRENT-LIMIT THRESHOLD vs. TEMPERATURE
VALLEY CURRENT-LIMIT THRESHOLD (mV) RILIM = 48.7k 130 120 110 100 90 80 70 60 -40 -15 10 35 60 85
MAX5951 toc11
200 180 160 PHASE (deg) 140 120 100 80 60
350 300 250 200 150 100 50 500 1000 1500 2000 VILIM (mV) 2500 3000
140
40 10M
3500
TEMPERATURE (C)
6
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12V/5V Input Buck PWM Controller
Typical Operating Characteristics (continued)
(Typical Operating Circuits. VIN = 12V or VIN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 49.9k, RILIM = 48.7k, CREG = 2.2F, TA = +25C.)
DL, DH DRIVER ON-RESISTANCE vs. TEMPERATURE
MAX5951 toc12
MAX5951
QUIESCENT SUPPLY CURRENT vs. TEMPERATURE
MAX5951 toc13
SWITCHING SUPPLY CURRENT vs. TEMPERATURE
MAX5951 toc14
2.00 VFB = 0.9V 1.75 DRIVER ON-RESISTANCE () 1.50 1.25 1.00 0.75 0.50 RESISTANCE SINKING
3.25
6.75
3.00 VPWM_IN = 16V IQ (mA)
6.50 VPWM_IN = 16V ISW (mA) 6.25 VPWM_IN = 12V
RESISTANCE SOURCING
2.75 VPWM_IN = 12V
2.50
6.00
2.25 0.25 0 -40 -15 10 35 60 85 TEMPERATURE (C) 2.00 -40
5.75
-15
10
35
60
85
5.50 -40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
PGOOD SEQUENCING (FIGURE 1)
MAX5951 toc15a
STARTUP SEQUENCING (FIGURE 1)
MAX5951 toc15b
DCENI 5V/div OUT1 1V/div OUT2 1V/div OUT3 1V/div
DCENI_ = STARTUP 5V/div OUT1 1V/div OUT2 1V/div OUT3 1V/div
PGI = PGOOD3 5V/div PGOOD3 5V/div 1ms/div PWREN SWITCHING FROM HIGH TO LOW PWREN SWITCHING FROM HIGH TO LOW 2ms/div
TRACKING (FIGURE 1)
MAX5951 toc15c
OVERLOAD RESPONSE
MAX5951 toc16a
DCENI_ = STARTUP 5V/div OUT1 1V/div OUT2 1V/div OUT3 1V/div 0V PGOOD_ 5V/div 0V 0A 0A OUT1 1V/div IOUT1 2A/div LX 10V/div DL 10V/div STARTUP 5V/div 4s/div
0V 400s/div PWREN SWITCHING FROM HIGH TO LOW
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7
12V/5V Input Buck PWM Controller MAX5951
Typical Operating Characteristics (continued)
(Typical Operating Circuits. VIN = 12V or VIN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 49.9k, RILIM = 48.7k, CREG = 2.2F, TA = +25C.)
OVERLOAD RESPONSE (HICCUP MODE)
MAX5951 toc16b
SHORT-CIRCUIT RESPONSE
MAX5951 toc17a
OUT1 1V/div IOUT1 2A/div LX 10V/div DL 10V/div STARTUP 5V/div 400s/div
OUT1 SHORTED TO PGND 1V/div
LX 10V/div DL 5V/div STARTUP 5V/div 2s/div
SHORT-CIRCUIT RESPONSE (HICCUP MODE)
MAX5951 toc17b
SYNCHRONIZATION
MAX5951 toc18
OUT1 SHORTED TO PGND 1V/div IOUT1 2A/div
SYNCIN2 = SYNCOUT1 5V/div
LX 5V/div
LX 10V/div DL 10V/div STARTUP 5V/div 400s/div 200ns/div DL 5V/div
BREAK-BEFORE-MAKE TIME
MAX5951 toc19a
BREAK-BEFORE-MAKE TIME
MAX5951 toc19b
LX1 5V/div
LX1 10V/div
DL1 5V/div IOUT = 0.5A 10ns/div 10ns/div
DL1 5V/div
8
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12V/5V Input Buck PWM Controller
Typical Operating Characteristics (continued)
(Typical Operating Circuits. VIN = 12V or VIN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 49.9k, RILIM = 48.7k, CREG = 2.2F, TA = +25C.)
EFFICIENCY vs. LOAD CURRENT
MAX5951 toc20
MAX5951
EFFICIENCY vs. LOAD CURRENT
90 80 EFFICIENCY (%) 70 60 50 40 30 20 VPWM_IN = 16V VPWM_IN = 12V VPWM_IN = 8V VPWM_IN = 5V
MAX5951 toc21
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 VOUT = 3.3V VPWM_IN = 8V VPWM_IN = 12V VPWM_IN = 5V VPWM_IN = 16V
100
10 0 0 0.2 0.4 0.6
VOUT = 2.5V 0.8 1.0
1.0
ILOAD (A)
ILOAD (A)
EFFICIENCY vs. LOAD CURRENT
90 80
EFFICIENCY (%)
LOAD-TRANSIENT RESPONSE
MAX5951 toc23 MAX5951 toc22
100 VIN = 5V VIN = 8V
IOUT1 1A/div
70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 ILOAD (A) VOUT = 1.2V
400s/div
VIN = 16V VIN = 12V
VOUT1 50mV/div AC-COUPLED
LOAD-TRANSIENT RESPONSE
MAX5951 toc24
1.25A 0A
IOUT1 1A/div
VOUT1 20mV/div AC-COUPLED
400s/div
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9
12V/5V Input Buck PWM Controller MAX5951
Pin Description
PIN 1, 5 NAME IN FUNCTION Supply Input Connection. Connect to an external voltage source from 8V to 16V. For 5V input application, connect IN = REG to a 5V 10% source. Connect an external divider from IN to PUVLO to AGND to lower the startup voltage. PWM UVLO Divider Center Point. Use an external divider to override the internal PWM UVLO divider. The rising threshold is set to 1.220V with 122mV hysteresis. Leave PUVLO unconnected for the default PWM UVLO. No Connection. Do not connect. DC-DC Enable Input. DCENI must be above VTHRESH for the PWM controller to start. Connect to REG if not used. DC-DC Enable Input Threshold Set. Connect a resistive divider from REG to THRESH to AGND to set the DCENI threshold. Connect to ground for a default threshold of 1.220V. Analog Ground Connection. Solder the exposed pad to a large AGND plane. Connect AGND and PGND together at one point near the input bypass capacitor return terminal. Synchronization Output. SYNCOUT is a synchronization signal to drive the SYNCIN of a second MAX5950 or MAX5951, if used. Leave SYNCOUT unconnected when not used. Synchronization Input. SYNCIN accepts the SYNCOUT from another MAX5950 or MAX5951 and shifts switching by 180, allowing the reduction of the input bypass capacitors. When used, drive with a frequency at least 20% higher than the frequency programmed through the RT pin. If phase staggering is desired, use 50% duty cycle. Connect SYNCIN to AGND when not used. Oscillator Timing Resistor Connection. Connect a 500k to 50k resistor from RT to AGND to program the switching frequency from 100kHz to 1MHz. Startup Input. STARTUP coordinates simultaneous soft-start for multiple converters. See the Tracking (STARTUP) section. Power-Good Output. PGOOD output goes high when SENSE is above VREF and STARTUP is high. Error-Amplifier Output. Connect COMP to the compensation feedback network. Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter output to AGND to set the output voltage. The FB voltage regulates to the reference voltage. Output Voltage Sense. Connect a resistive divider from the converter output to SENSE to AGND to monitor the programmed output voltage. SENSE is compared to the internal reference, VREF. Valley Current-Limit Set Output. Connect a 25k to 175k resistor, RILIM, from ILIM to AGND to program the valley current-limit threshold from 50mV to 350mV. ILIM sources 20A out to RILIM. The resulting voltage divided by 10 is the valley current limit. Alternatively, a resistive divider from REG to ILIM to AGND can be used to set the valley current limit.
2 3, 4, 6-11 12 13 14 15
PUVLO N.C. DCENI THRESH AGND SYNCOUT
16
SYNCIN
17 18 19 20 21 22
RT STARTUP PGOOD COMP FB SENSE
23
ILIM
10
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12V/5V Input Buck PWM Controller
Pin Description (continued)
PIN 24 25 26 27 28 29 30 31 32 EP NAME CS+ CSPGND DL DREG LX DH BST REG EP FUNCTION Positive Current-Sense Input. Connect CS+ to the synchronous MOSFET source (connected to PGND). Negative Current-Sense Input. Connect CS- to the synchronous MOSFET drain (connected to LX). Power-Ground Connection. Connect the input filter capacitor's negative terminal, the source of the synchronous MOSFET, and the output filter capacitor's return to PGND. Connect externally to AGND at a single point near the input capacitor return terminal. Low-Side Gate-Driver Output. DL is the gate-driver output for the synchronous MOSFET. Gate-Drive Supply for the Low-Side MOSFET Driver. Connect externally to REG and the anode of the boost diode. Source Connection of the High-Side MOSFET and Drain Connection of the Synchronous MOSFET. Connect the inductor and the negative side of the boost capacitor to LX. High-Side Gate-Driver Output. DH drives the gate of the high-side MOSFET. High-Side Gate-Driver Supply. Connect BST to the cathode of the boost diode and to the positive terminal of the boost capacitor. 5V Regulator Output. Bypass with a 2.2F ceramic capacitor to AGND. Exposed Pad. Connect the exposed pad to AGND.
MAX5951
Detailed Description
The MAX5951 is a PWM, step-down, DC-DC controller. The device operates over the input-voltage range of 8V to 16V or 5V 10% (V IN = V REG ) and provides an adjustable output from 0.8V to 5.5V. The device delivers up to 10A of load current with excellent load-andline regulation. The MAX5951 PWM controller utilizes a voltage-mode control scheme for good noise immunity and offers external compensation allowing for maximum flexibility with a wide selection of inductor values and capacitor types. The device operates at a fixed switching frequency that is programmable from 100kHz to 1MHz and can be synchronized to an external clock signal through the SYNC input. The device includes UVLO and digital soft-start. Protection features include valleymode current limit, hiccup-mode output short-circuit protection, and thermal shutdown.
PWM Controller
PWM UVLO
VIN must exceed the default PWM UVLO threshold (7V typ) before any PWM operation can commence. The UVLO circuitry keeps the MOSFET drivers, oscillator, and all the internal circuitry shut down to reduce current consumption. Override the internal PWM UVLO divider by connecting an external resistive divider from IN to PUVLO to AGND. The PUVLO threshold is 1.220V with 122mV hysteresis.
Digital Soft-Start
The MAX5951 soft-start feature allows the load voltage to ramp up in a controlled manner, eliminating output voltage overshoot. Soft-start begins after VIN exceeds the UVLO threshold. The soft-start circuitry gradually ramps up the reference voltage. This controls the rate of rise of the output voltage and reduces input surge currents during startup. The soft-start duration is 1024 clock cycles. The output voltage is incremented through 128 equal steps. The output reaches regulation when soft-start is completed, regardless of output capacitance and load.
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11
12V/5V Input Buck PWM Controller MAX5951
Internal Linear Regulator (REG)
REG is the output terminal of a 5V LDO, which is powered from IN and provides power to the IC. Bypass REG to AGND with a 2.2F ceramic capacitor. Place the capacitor physically close to the MAX5951 to provide good bypassing. REG is intended for powering only the internal circuitry and should not be used to supply power to external loads. synchronization. For proper synchronization, the external frequency must be at least 20% higher than the frequency programmed through the RT input. If SYNCIN is 50% duty cycle, SYNCOUT is shifted by 180, allowing the reduction of the DC-DC converter input bypass capacitor. SYNCOUT is a synchronization signal that is used to drive the SYNCIN of a second MAX5950 or MAX5951.
Low-Side MOSFET Driver Supply (DREG)
DREG is the supply input for the low-side MOSFET driver. Connect DREG to REG externally. Adding an RC filter (5 resistor and 2.2F ceramic capacitor) from REG to DREG filters out the high peak currents of the MOSFET drivers.
Tracking (STARTUP)
The STARTUP input in conjunction with digital soft-start provides simple ratiometric tracking. When using multiple MAX5950s or MAX5951s, in addition to connecting SYNCIN and SYNCOUT signals appropriately, connect the STARTUP of all the devices together. STARTUP synchonizes the soft-start of all the devices' references, and hence their respective output voltages track ratiometrically. See Figure 1 and the Typical Operating Circuits. The STARTUP input has an internal 10A pullup current, but can be driven by external logic. When using multiple converters, connect the STARTUP of all the devices together.
High-Side MOSFET Driver Supply (BST)
BST supplies the power for the high-side MOSFET drivers. Connect the bootstrap diode from BST to DREG (anode at DREG and cathode at BST). Connect a bootstrap 1F ceramic capacitor between BST and LX.
MOSFET Gate Drivers (DH, DL)
The high-side (DH) and low-side (DL) drivers drive the gates of the external n-channel MOSFETs. The drivers' 2A peak source-and-sink current capability provides ample drive to ensure fast rise and fall times of the switching MOSFETs. Short rise and fall times minimize switching losses. For low output-voltage applications where the duty cycle is less than 50%, choose a highside MOSFET (Q2) with a moderate RDS(ON). Choose a low-side MOSFET (Q1) with a very low RDS(ON). The gate driver circuitry also provides a break-beforemake time (25ns, typ) to prevent shoot-through currents during transition.
Startup Sequencing (DCENI, THRESH)
The DCENI input must be above VTHRESH for the PWM controller to start. By connecting the DCENI inputs of multiple devices together and having different start thresholds (VTHRESH_), the startup of the PWM controllers can be staggered to provide power sequencing. Connect a resistive divider from REG to THRESH to AGND to set the start thresholds of each device. Connect THRESH to AGND to produce a default 1.220V threshold for DCENI. See Figure 1 and the Typical Operating Circuits.
Oscillator/Synchronization Input (SYNCIN)/ Synchronization Output (SYNCOUT)
Use an external resistor at RT to program the MAX5951 switching frequency from 100kHz to 1MHz. Choose the appropriate resistor at RT to calculate the desired output switching frequency (fSW): fSW (Hz) = (5 x 1010) / RRT () Connect an external clock (SYNCOUT from another MAX5950 or MAX5951) at SYNCIN for external clock
Power-Good Sequencing (PGOOD, SENSE)
The PGOOD outputs and DCENI inputs can be daisychained to generate power sequencing. The PGOOD output is pulled high when the voltage at SENSE is above VREF (800mV, typ). Connect a resistive divider from the power-supply output voltage to SENSE to AGND to set the power-good threshold. See Figure 1 and the Typical Operating Circuits.
12
______________________________________________________________________________________
12V/5V Input Buck PWM Controller MAX5951
TRACKING DCEN1 DCENI1
STARTUP SEQUENCING DCEN1 REG1
PGOOD SEQUENCING
THRESH1 THRESH1 PGOOD1
THRESH1
PGOOD1 PGOOD1 DCENI2 DCENI2
DCENI2
THRESH2
REG2
THRESH2
PGOOD2 THRESH2 DCENI3 PGOOD2
DCENI3 THRESH3 PGOOD2 THRESH3 DCENI3 PGOOD3 REG3 PGOOD3 STARTUP1 THRESH3 STARTUP2 STARTUP1
STARTUP3 PGOOD3 STARTUP1
STARTUP2
STARTUP3
STARTUP2 STARTUP3 CSTART
Figure 1. Tracking, STARTUP Sequencing, and PGOOD Sequencing Configurations
______________________________________________________________________________________
13
12V/5V Input Buck PWM Controller MAX5951
Error Amplifier
The output of the internal error amplifier (COMP) is available for frequency compensation (see the Compensation Design Guidelines section). The inverting input is FB; the output is COMP. The error amplifier has an 80dB open-loop gain and a 2.5MHz GBW product. See the Typical Operating Characteristics for the Open-Loop Gain and Phase vs. Frequency graph. count of NCL is cleared (see Figure 2). Hiccup mode protects against continuous output short circuit.
Thermal-Overload Protection
The MAX5951 features an integrated thermal-overload protection with temperature hysteresis. Thermal-overload protection limits the total power dissipation in the device and protects it in the event of an extended thermal fault condition. When the die temperature exceeds +135C, an internal thermal sensor shuts down the device, turning off the power MOSFETs and allowing the die to cool. After the die temperature falls by +15C, the part restarts with a soft-start sequence.
PWM Comparator
An internal ramp is compared against the output of the error amplifier to generate the PWM signal. The amplitude of the ramp, VRAMP, is 1.8V.
Output Short-Circuit Protection (Hiccup Mode)
The current-limit circuit employs a lossless valley current-limiting algorithm that uses the MOSFET's on-resistance as the current-sensing element. Once the high-side MOSFET turns off, the voltage across the lowside MOSFET is monitored. If the voltage across the low-side MOSFET (R DS(ON) x I INDUCTOR ) does not exceed the current-limit threshold, the high-side MOSFET turns on normally at the start of the next cycle. If the voltage across the low-side MOSFET exceeds the current-limit threshold just before the beginning of a new PWM cycle, the controller skips that cycle. During severe overload or short-circuit conditions, the switching frequency of the device appears to decrease because the on-time of the low-side MOSFET extends beyond a clock cycle. If the current-limit threshold is exceeded for eight cumulative clock cycles (NCL), the device shuts down (both DH and DL are pulled low) for 512 clock cycles (hiccup timeout) and restarts with a soft-start sequence. If three consecutive cycles pass without a current-limit event, the
PWM Controller Design Procedures
Setting the Undervoltage Lockout
Connect an external resistive divider from IN to PUVLO to AGND to override the internal PWM UVLO divider. The rising threshold at PUVLO is set to 1.220V with 120mV hysteresis. First select the PUVLO to AGND resistor (R2), then calculate the resistor from IN to PUVLO (R1) using the following equation: VIN R1 = R2 x - 1 VPUVLO where VIN is the input voltage at which the converter needs to turn on, VPUVLO = 1.220V, and R2 is chosen to be less than 20k. See Figure 3. Leave PUVLO unconnected for the default PWM UVLO threshold. In this case, an internal voltage-divider monitors the supply voltage at IN and allows startup when IN rises above 7V (typ).
IN COUNT OF 8 NCL INITIATE HICCUP TIMEOUT NHT PUVLO
CURRENT LIMIT
IN
R1
CLR
IN
COUNT OF 3 NCLR
R2
CLR
Figure 2. Hiccup Block Diagram 14
Figure 3. External PWM UVLO Divider
______________________________________________________________________________________
12V/5V Input Buck PWM Controller
Setting the Output Voltage
Connect a resistive divider from OUT to FB to AGND to set the output voltage. First, calculate the resistor from OUT to FB using the guidelines in the Compensation Design Guidelines section. Once R3 is known, calculate R4 using the following equation: R4 = R3 VOUT - 1 VFB
Input Capacitor Selection
The discontinuous input current of the buck converter causes large input ripple currents; therefore, the input capacitor must be carefully chosen to withstand the input ripple current and maintain the input voltage ripple within design requirements. The total voltage ripple is the sum of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the input capacitor), which peaks at the end of the on cycle. Calculate the input capacitance and ESR required for a specified ripple using the following equations: ESR = VESR IP -P ILOAD(MAX) + 2
MAX5951
where VFB = 0.8V.
Inductor Selection
Three key inductor parameters must be specified for operation with the MAX5951: inductance value (L), peak inductor current (IPEAK), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current (IP-P). Higher IP-P allows for a lower inductor value. A lower inductance value minimizes size and cost and improves largesignal and transient response, but reduces efficiency due to higher peak currents and higher peak-to-peak output voltage ripple for the same output capacitor. A higher inductance increases efficiency by reducing the ripple current; however, resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels especially when the inductance is increased without also allowing for larger inductor dimensions. A good rule of thumb is to choose IP-P equal to 30% of the full-load current. Calculate the inductor using the following equation: L= VOUT (VIN - VOUT ) VIN x fSW x IP-P
V ILOAD(MAX) x OUT VIN CIN = VQ x fSW where IP -P = (VIN - VOUT ) x VOUT VIN x fSW x L
ILOAD(MAX) is the maximum output current, IP-P is the peak-to-peak inductor current, and fSW is the switching frequency. The MAX5951 includes UVLO hysteresis to avoid possible unintentional chattering during turn-on. Use additional bulk capacitance if the input source impedance is high. When the input voltage is near the UVLO, additional input capacitance helps avoid possible undershoot below the UVLO threshold during transient loading.
Output Capacitor Selection
The allowed output-voltage ripple and the maximum deviation of the output voltage during load steps determine the required output capacitance and its ESR. The output ripple is mainly composed of VQ (caused by the capacitor discharge) and VESR (caused by the voltage drop across the ESR of the output capacitor). The equations for calculating the peak-to-peak outputvoltage ripple are: IP-P 8 x COUT x fSW I VESR = ESR x P-P 2 VQ = VESR and VQ are not directly additive since they are out of phase from each other. If using ceramic capacitors, which generally have low ESR, VQ dominates. If using electrolytic capacitors, VESR dominates.
15
VIN and VOUT are typical values so that efficiency is optimum for typical conditions. The switching frequency is programmable between 100kHz and 1000kHz (see the Oscillator/Synchronization Input (SYNCIN)/ Synchronization Output (SYNCOUT) section). The peak-to-peak inductor current, which reflects the peakto-peak output ripple, is worst at the maximum input voltage. See the output capacitor selection section to verify that the worst-case output current ripple is acceptable. The inductor saturation current (ISAT) is also important to avoid runaway current during continuous output short-circuit conditions. Select an inductor with an ISAT specification higher than the maximum peak current.
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12V/5V Input Buck PWM Controller
The allowable deviation of the output voltage during load transients also affects the choice of capacitance, its ESR, and its equivalent series inductance (ESL). The output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. The response time (tRESPONSE) depends on the closed-loop bandwidth of the converter (see the Compensation Design Guidelines section). The resistive drop across the output capacitor's ESR, the drop across the capacitor's ESL, and the capacitor discharge cause a voltage droop during the load-step. Use a combination of low-ESR tantalum/aluminum electrolyte and ceramic capacitors for better load transient and voltage ripple performance. Surface-mount capacitors and capacitors in parallel help reduce the ESL. Keep maximum output-voltage deviation below the tolerable limits of the electronics being powered. Use the following equations to calculate the required ESR, ESL, and capacitance value during a load step: ESR = VESR ISTEP xt I COUT = STEP RESPONSE VQ VESL x t STEP ISTEP
MAX5951
The 20A current source, ILIM reference current, has a temperature coefficient of 3333ppm/C. This allows the valley current-limit threshold: RILIM x 20A(T) 10 to track and compensate for the increase in the synchronous MOSFET's RDS(ON) with increasing temperature. MOSFETs typically have a temperature coefficient range within 3000ppm/C to 7000ppm/C. Refer to the MOSFET data sheet for a device-specific temperature coefficient. At a given temperature, the calculated VVALLEY must be less than the minimum valley current-limit threshold specified. Figure 4 illustrates the effect of MAX5951 ILIM reference current temperature coefficient to compensate for the variation of the MOSFET RDS(ON) over the operating junction temperature range.
Power MOSFET Selection
When selecting the MOSFETs, consider the total gate charge, R DS(ON) , power dissipation, the maximum drain-to-source voltage, package thermal impedance, and desired current limit. The product of the MOSFET gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. Choose MOSFETs optimized for high-frequency switching applications. The average gate-drive current from the MAX5951's output is proportional to the frequency and gate charge required to drive the MOSFET. The power dissipated in the MAX5951 is proportional to the input voltage and the average drive current (see the Power Dissipation section).
VALLEY CURRENT-LIMIT THRESHOLD AND RDS(ON) vs. TEMPERATURE
1.5 1.4 1.3 VILIM AND RDS(ON) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -40 -15 10 35 60 85 TEMPERATURE (C) VILIM RDS(ON)
ESL =
where ISTEP is the load step, tSTEP is the rise time of the load step, and tRESPONSE is the response time of the controller.
Setting the Current Limit
Connect a 25k to 175k resistor, RILIM, from ILIM to AGND to program the valley current-limit threshold between 50mV and 350mV. ILIM sources 20A out to RILIM. The resulting voltage divided by 10 is the valley current-limit threshold. The MAX5951 uses a valley current-sense method for current limiting. The voltage drop across the low-side MOSFET due to its on-resistance is used to sense the inductor current. The voltage drop across the low-side MOSFET at the valley point and at ILOAD(MAX) is: I VVALLEY = RDS(ON) (T) x ILOAD(MAX) - P-P 2 RDS(ON) is the on-resistance of the low-side MOSFET, which is temperature dependent, I LOAD(MAX) is the maximum DC load current, and IP-P is the peak-topeak inductor current.
Figure 4. Current-Limit Threshold and RDS(ON) vs. Temperature 16 ______________________________________________________________________________________
12V/5V Input Buck PWM Controller
Compensation Design Guidelines
The MAX5951 uses a voltage-mode control scheme that regulates the output voltage by comparing the error amplifier output (COMP) with an internal ramp to produce the required duty cycle. The output lowpass LC filter creates a double pole at the resonant frequency, which has a gain drop of -40dB/decade. The compensation network must compensate for this gain drop and phase shift in order to achieve a stable closed-loop system. The basic regulator loop consists of a power modulator, an output feedback divider, and a voltage-error amplifier. The power modulator has a DC gain set by VIN/VRAMP, with a double pole and a single zero set by the output inductance (L), the output capacitance (C OUT ), and its equivalent series resistance (ESR). Below are equations that define the power modulator: GMOD(DC) = fLC = VIN VRAMP 1 1 2 x COUT x RESR The switching frequency is programmable between 100kHz and 1000kHz by an external resistor at RT. The crossover frequency (fC), which is the frequency when the closed-loop gain is equal to unity, should be set to fSW / 10 or fGBW / 25, whichever is lower. The error amplifier must provide a gain-and-phase boost to compensate for the rapid gain-and-phase loss from the LC double pole. This is accomplished by utilizing type 3 compensation (see Figures 5 and 6) that introduces two zeros and three poles into the control loop. The error amplifier has a low-frequency pole (fP1) at the origin; two zeros at: 1 fZ1 = 2 x R5 x C7 and: fZ2 = 1 2 x R3 x C6
MAX5951
2 L x COUT
and higher frequency poles at: 1 fP2 = 2 x R6 x C6 and: fP3 = 1 2 x R5 x C8
C8
fZESR =
C8
R5 C6 R6 R3 VOUT R4 REF EA
C7 C6 R6 R3 VOUT COMP R4 REF
R5
C7
EA
COMP
GAIN (dB)
CLOSED-LOOP GAIN EA GAIN
GAIN (dB)
CLOSED-LOOP GAIN
EA GAIN
fZ1 fZ2
fC
fP2 fP3
FREQUENCY
fZ1 fZ2
fP2
fC
fP3
FREQUENCY
Figure 5. Error-Amplifier Compensation Circuit (Closed-Loop and Error-Amplifier Gain Plot) for Ceramic Capacitors
Figure 6. Error-Amplifier Compensation Circuit (Closed-Loop and Error-Amplifier Gain Plot) for Higher ESR Output Capacitors 17
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12V/5V Input Buck PWM Controller
Compensation when fC < fZESR Figure 5 shows the error-amplifier feedback, as well as its gain response for circuits that use low-ESR output capacitors (ceramic). In this case, fC occurs before fZESR. fZ1 is set to 0.5 x fLC and fZ2 is set to fLC in order to compensate for the gain-and-phase loss due to the double pole. Choose the inductor (L) and output capacitor (C OUT ) as described in the Inductor Selection and Output Capacitor Selection sections. Pick a value for the feedback resistor R5 in Figure 5 (values between 1k and 10k are adequate). C7 is then calculated as: C7 = 1 2 x 0.5 x fLC x R5 Compensation when fC > fZESR For larger ESR capacitors such as tantalum and aluminum electrolytic, fZESR can occur before fC. If fC > fZESR, then fC occurs between fP2 and fP3. fZ1 and fZ2 remain the same as before; however, fP2 is now set equal to fZESR. The output capacitor's ESR zero frequency is higher than fLC but lower than the closedloop crossover frequency. The equations that define the error amplifier's poles and zeros (fZ1, fZ2, fP1, fP2, and fP3) are the same as before. However, fP2 is now lower than the closed-loop crossover frequency. Figure 5 shows the error-amplifier feedback, as well as its gain response for circuits that use higher ESR output capacitors (tantalum, aluminum electrolytic, etc.). Pick a value for feedback resistor R5 in Figure 5 (values between 1k and 10k are adequate). C7 is then calculated as: 1 C7 = 2 x 0.5 x fLC x R5 The circuit is implemented with C7 >> C8 and R3 >> R6, in which case the error-amplifier gain between fP2 and fP3 is approximately equal to: R5 R6 The modulator gain at fC is: GMOD(fC) = GMOD(DC) (2)2 x L x COUT x fC2
MAX5951
fC occurs between fZ2 and fP2. The circuit is implemented with C7 >> C8 and R3 >> R6, in which case, the error amplifier gain (GEA) at fC is due primarily to C6 and R5. Therefore: GEA(fc) = 2 x fC x C6 x R5 The modulator gain at fC is: GMOD(fC) = GMOD(DC) (2)2 x L x COUT x fC2
Since GEA(fC) x GMOD(fC) = 1, C6 is calculated by: f x L x COUT x 2 C6 = C R5 x GMOD(DC) R3 is then calculated as: R3 1 2 x fLC x C6
Since GEA(fC) x GMOD(fC) = 1, R6 can then be calculated as: R6 R5 x GMOD(DC) (2)2 x L x COUT x fC2
fP2 is set at 1/2 the switching frequency (fSW). R6 is then calculated by: 1 R6 = 2 x C6 x 0.5 x fSW fP3 is set at 5 x fC. Therefore, C8 is calculated as: 1 C8 = 2 x R5 x 5 x fC
fP2 is set to fZESR. C6 is then calculated as: C x ESR C6 = OUT R6 R3 is then calculated as: R3 1 2 x fLC x C6
fP3 is set at 5 x fC. Therefore, C8 is calculated as: C8 = 1 2 x R5 x 5 x fC
18
______________________________________________________________________________________
12V/5V Input Buck PWM Controller
PWM Controller Applications Information
Power Dissipation
The 32-pin TQFN thermally enhanced package can dissipate 2.7W. Calculate power dissipation in the MAX5951 as a product of the input voltage and the total REG output current (IREG). IREG includes quiescent current (IQ) and gate drive current (IDREG): PD = VIN x IREG IREG = IQ + [fSW x (QG1 + QG2)] where QG1 and QG2 are the total gate charge of the low-side and high-side external MOSFETs. fSW is the switching frequency of the converter, and IQ is the quiescent current of the device at the switching frequency. Use the following equation to calculate the maximum power dissipation (PDMAX) in the chip at a given ambient temperature (TA): PDMAX = 34.5 x (150 - TA) 3) Keep short the current loop formed by the synchronous switching MOSFET, inductor, and output capacitor. 4) Keep AGND and PGND isolated and connect them at one single point close to the negative terminal of the input filter capacitor. 5) Run the current-sense lines CS+ and CS- close to each other to minimize the loop area. 6) Avoid long traces between the REG/DREG bypass capacitors, driver output of the MAX5951, MOSFET gates, and PGND. Minimize the loop formed by the REG bypass capacitors, bootstrap diode, bootstrap capacitor, the MAX5951, and the upper MOSFET gate. 7) Place the bank of output capacitors close to the load. 8) Distribute the power components evenly across the board for proper heat dissipation. 9) Provide enough copper area at and around the switching MOSFETs and inductor to aid in thermal dissipation. 10) Use 2oz copper to keep the trace inductance and resistance to a minimum. Thin copper PC boards can compromise efficiency since high currents are involved in the application. Also, thicker copper conducts heat more effectively, thereby reducing thermal impedance.
MAX5951
PC Board Layout Guidelines
Use the following guidelines to lay out the switching voltage regulator: 1) Place the IN and DREG bypass capacitors close to the MAX5951 PGND pin. Place the REG bypass capacitor close to the AGND pin. 2) Minimize the area and length of the high-current loops from the input capacitor, upper switching MOSFET, inductor, and output capacitor back to the input capacitor negative terminal.
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19
12V/5V Input Buck PWM Controller MAX5951
Simplified Block Diagram
PWM CONTROLLER
PWM_IN
PUVLO
THRESH
DCENI
MAX5951 LDO REG EN 1.220V VREGOK STARTUP 0.8V REF RES CSSHDN CLK DIGITAL SOFT-START E/A FB DH R COMP SYNCIN RT EN RAMP OSC 0.3V CLK PGND STARTUP REF CPWM IMAX SET DOMINANT S Q REG 10A LX DREG DL RES OVERLOAD OVL MANAGEMENT IMAX CLK CURRENTLIMIT SET ILIM THERMAL SHDN REG 10A AGND
CS+
REF
BST
SYNCOUT
SENSE
PGOOD
20
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12V/5V Input Buck PWM Controller
Typical Operating Circuits
TRACKING
+12V
MAX5951
CIN
CBST IN REG DREG BST DH Q2 L LX CSPUVLO VOUT1
MAX5951
DL CS+
Q1
COUT
C6
R3
R6
THRESH
PGND FB DCENI AGND PGOOD SYNCIN SYNCOUT RRT RT ILIM STARTUP RILIM R5 COMP SENSE C8 C7 R4
CBST IN REG DREG BST DH Q2 L LX CSPUVLO VOUT2
MAX5951
DL CS+
Q1
COUT
C6
R3
R6
THRESH
PGND FB
DCENI
AGND
PGOOD SYNCIN
SYNCOUT
RT
ILIM STARTUP
COMP
SENSE
C8 C7 R5 R4
RRT
RILIM
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21
12V/5V Input Buck PWM Controller MAX5951
Typical Operating Circuits (continued)
+12V
STARTUP SEQUENCING
CIN
CBST IN REG DREG BST DH Q2 L LX CSPUVLO VOUT1
MAX5951
DL CS+
Q1
COUT
C6
R3
R6
THRESH
PGND FB
DCENI
AGND
PGOOD
SYNCIN SYNCOUT RRT
RT
ILIM
STARTUP RILIM
COMP
SENSE
C8 C7 R5 R4
CBST IN REG DREG BST DH Q2 L LX CSPUVLO VOUT2
MAX5951
DL CS+
Q1
COUT
C6
R3
R6
THRESH
PGND FB
DCENI
AGND
PGOOD
SYNCIN
SYNCOUT
RT
ILIM STARTUP
COMP
SENSE
C8 C7 R5 R4
RRT
RILIM
22
______________________________________________________________________________________
12V/5V Input Buck PWM Controller
Typical Operating Circuits (continued)
PGOOD SEQUENCING
+12V
MAX5951
CIN
CBST IN REG DREG BST DH Q2 L LX CSPUVLO VOUT1
MAX5951
DL CS+
Q1
COUT
C6
R3
R6
THRESH
PGND FB DCENI AGND PGOOD SYNCIN SYNCOUT RRT RT ILIM STARTUP RILIM R5 COMP SENSE C8 C7 R4
CBST IN REG DREG BST DH Q2 L LX CSVOUT2
MAX5951
THRESH PUVLO DCENI AGND PGOOD SYNCIN SYNCOUT RT ILIM STARTUP COMP
DL CS+ PGND FB SENSE C8
Q1
COUT
C6
R3
R6
RRT
RILIM R5
C7
R4
______________________________________________________________________________________
23
12V/5V Input Buck PWM Controller MAX5951
Typical Operating Circuits (continued)
ALTERNATE CURRENT SENSE
+12V
CIN
CBST IN REG DREG BST DH Q2 L LX DL PUVLO Q1 COUT C6 R3 VOUT1
MAX5951
CS-
THRESH
CS+ PGND FB
R6
DCENI
AGND
PGOOD
SYNCIN SYNCOUT RT
ILIM
STARTUP
COMP
SENSE
C8 R4 R5 C7
RRT
Chip Information
PROCESS: BiCMOS
24
______________________________________________________________________________________
12V/5V Input Buck PWM Controller
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 D D/2 MARKING k L
C L
MAX5951
b D2/2
0.10 M C A B
AAAAA
E/2 E2/2 E (NE-1) X e
C L
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
1 2
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-2 T1655-3 T1655N-1 T2055-3
D2
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3 3.00 3 3.00 3.00 3.00 3.20
E2
exceptions
L
MIN. NOM. MAX. MIN. NOM. MAX. 0.15
DOWN BONDS ALLOWED
A A1 A3 b D E e k L
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.40 BSC. 0.50 BSC.
- 0.25 - 0.25 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 L1 - 0.30 0.40 0.50 16 40 N 20 28 32 ND 4 10 5 7 8 4 10 5 7 8 NE WHHB ----WHHC WHHD-1 WHHD-2 JEDEC
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
3.00 3.00 3.00 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** **
YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES
** SEE COMMON DIMENSIONS TABLE
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
M. Quijano
QFN THIN.EPS

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